Circuit testing is an essential step in the production of digital circuits. After the circuit is manufactured, and prior to shipping to users, the circuit is electronically tested by a computerized tester to verify that no faults exist in the circuitry. A sequence of test values are input to the circuit and the resulting values are sensed at the circuit outputs in order to verify the proper operation of the circuit.
The classical approach to testing a circuit is to represent the circuit to be tested as a network of logical primitive elements of a restricted set of types (i.e., AND-gates, OR-gates, inverters, NAND-gates, NOR-gates, flip flops, etc.). Modelling such circuits becomes impractical, however, when the circuit to be tested is large. The task of generating a test sequence becomes especially difficult when a complex functional block is embedded into the circuit. In such cases, in addition to the test sequence designer having to generate a suitable set of test signals for the embedded cell, the programmer must formulate appropriate access procedures. An example of such a circuit is a large memory array embedded within a microprocessor chip.
In order to streamline the process for generating test programs for digital circuits containing embedded functional blocks, circuit test designers have typically adopted the modular approach. This method entails designing test procedures for specific types of blocks and then merging these test procedures with a customized program for transferring the test sequences from the primary input pins of the digital circuit to the inputs of the functional block to be tested and then transferring the output values from the functional block to the primary output pins of the circuit.
In the aforementioned approach to test generation, once the test generation procedures for the types of embedded functional blocks have been designed, the primary problem faced by the test program designer is formulating the set of input signals to the primary inputs which will propagate the test input signals from the input pins of the circuit to the inputs of the embedded block and transport the output signals from the outputs of the embedded block to the primary output pins of the digital circuit.
The problem of generating test sequences for embedded functional blocks in a digital circuit has been given much attention. The testing of embedded blocks requires both verification of the function of the embedded block and identification of a path from the primary inputs of the digital circuit to the inputs of the embedded block and of a path from the outputs of the embedded block to the primary outputs of the circuit.
Several well known methods have been developed for identification of the paths for delivering input signals to the embedded functional block and transferring output signals from the embedded functional block to the output pins of the tested digital circuit. One known method for generating test access procedures, called the "I-path" method, requires the identification of paths by means of which the input test signals can be propagated identically through the circuit to the embedded block. The use of the I-path approach to generating test access procedures is, however, often impractical, since many embedded circuits are not connected to the primary circuit inputs or outputs by I-paths.
A second known method for generating test access procedures is called the "T-path" method. The T-path method allows for transformation of the input values over the access path to the embedded block and transformation of the output values over the access path from the embedded block to the primary output pins of the digital circuit. For each set of input values there is only one set of output values and for each set of output values there is only one set of input values.
Another well known method for generating test access procedure is called the "F-path" method. The F-path approach to identification of access paths to and from an embedded block broadens the acceptable set of input values to any set of inputs which provides a one-to-one dependency between the values input and output at the primary I/O pins of the digital circuit while testing the embedded functional block for operational defects.
Though the aforementioned I-path, T-path and F-path methods present standards for identifying paths from primary inputs to the inputs of an embedded cell and from the outputs of the embedded cell to the primary outputs of the circuit (as well as algorithms for implementing the standards), these well known procedures fail to address the problem of providing an efficient method for automatic generation of test access procedures.
In addition to the previously described software approaches to circuit testing, certain hardware design methods have been developed that implement the I-path or T-path methods of test access procedures by utilizing special test access hardware in the circuit. This specialized hardware is inactive during the normal operation of the circuit. This hardware approach to generating test access procedures is known at the board design level as well. These well known hardware approaches solve the basic problem of providing access to embedded blocks, but suffer from the disadvantage of increased complexity in the circuit, as well as creation of circuit delays which cause additional problems for the test designer.
Other known methods for generating test access procedures have disadvantages in that they will only work in circuits that do not contain feedback loops or reconvergent fanout paths.
One technique for modeling sequential circuits is by means of "iterative arrays." This modeling technique maps the time domain response of a sequential circuit into a space domain response of the iterative array. This approach has been generally adopted for modeling sequential circuits for generating test procedures. For a general description of the iterative array model, please see Digital Circuit Testing and Testable Design, by M. Abramovici et al, Computer Science Press, 1990. For iterative array test procedure generation, a synchronous sequential circuit S can be modeled by a pseudocombinational iterative array. This iterative array consists of n copies C1, . . . , Cn of the combinational part C of the circuit S. This transformed circuit corresponds to the original circuit in the following manner. If in response to an input sequence x(0) . . . , x(n) applied to the circuit S in time frames 1 to n, circuit S produces the output sequence z(0), . . . , z(n) and moves into the states y(1), y(2), . . . , y(n+1), then in the iterative array model, every circuit C1, . . . , Cn will receive signals x(i), y(i) and generate output signals z(i) and y(i+1).
A general method for generating test access procedures is also known, utilizing the well known D-algorithm scheme on an iterative array model of sequential circuits to determine the T-paths for the circuit. State transition diagrams are used to calculate the conditions for justifying the activated paths. However, this general method is highly inefficient for sequential circuits of any practical size and/or complexity.
In the aforementioned general method, complex circuits are handled by either additional test hardware or by describing the circuit at the level of large functional subsystems for which T-path activation procedures have already been formulated. Furthermore, the general method does not take into consideration the possible sequential nature of the embedded block which introduces further timing problems when transporting the output values of the embedded block to the primary output pins of the circuit. Finally, the general method does not account for complex clocking schemes which often accompany many digital circuits and preclude modelling the circuit by iterative arrays.
Thus, it is an object of the present invention to provide a more efficient method for automatically generating access procedures for embedded functional blocks than has been previously known in the art.
Another object of the present invention is to provide a test access generation method which does not impose hardware design requirements on the tested circuit.